The invention relates to a method of manufacturing a semiconductor device. Recently, as a design rule of a semiconductor device has been rapidly reduced to less than a 100 nm class, correspondingly, the length and width of channel of a transistor is decreased. Additionally, the concentration of doping to a junction area is increased such that a junction leakage current according to an increment of electric field is increased. Thus, in a transistor structure having a conventional planer channel structure, it is difficult to obtain a desired threshold voltage Vt in a highly integrated device, while reaching uppermost limit in improving a refresh characteristic. Accordingly, implementation of a semiconductor device having various forms of recess channels capable of securing an effective channel length of a transistor and the implementation of a semiconductor device having a three-dimensional channel structure capable of extending a channel width and practical process development researches are actively progressing. However, in the process of implementing the semiconductor device having three-dimensional structure channel, a fault frequently happens.